As semiconductor devices have become more highly integrated, a line width and an interval of patterns constituting the semiconductor device may be narrowed. In accordance with the reduction in the line width of the pattern (that is, the design rule), the channel length of the transistor may be reduced.
To reduce a size of a semiconductor device while increasing the response speed thereof, a method of reducing the gate length has been used. As the gate length is reduced, the channel length, which may be a moving distance of a carrier, may also be reduced. A response speed and a level of integration of the semiconductor device may thus be improved.
Further, a method of reducing the Gate to Contact space has been suggested and may improve the level of integration of the semiconductor device.
The spacer that influences the gate and the contact area may be used to prevent a HCI (hot carrier injection) effect and a short channel effect and may reduce the resistance when forming the source/drain area. That is, the spacer may serve as a mask when the impurity implantation process is performed to form the source/drain area.
However, if the lower area of the space is enlarged when the spacer is formed in the gate, the contact may make contact with the spacer. This may change characteristics of the transistor.